The present invention relates to an analysis method for crosstalk between many aggressor wires in semiconductor integrated circuit devices and an electronic circuit device having such integrated circuit devices mounted on a printed circuit board or the like, a method for calculating delay times, a method for designing/manufacturing electronic circuit device by using the same, and the like.
In realizing a logic circuit, there is used up to now a method by which, after arranging large and small electronic circuits known as circuit cells or blocks (also called circuit units), each having a certain logical function, over a semiconductor integrated circuit chip, in a package or over a substrate, the input/output terminals of the cells or blocks are connected using metal wiring.
Since minimizing the area of the semiconductor IC chip, package module or substrate-mounted system to be designed would mean an economic advantage, it is desirable to maximize the integrating density or mounting density of the cells, blocks or wiring. For this reason, in the production of semiconductor integrated circuits, an ever higher degree of fineness has been sought in processing technique and, in respect of mounting techniques, ever greater density has been pursued in mounting within packages or over substrates. However, trying to house many elements or wires in a limited area gives rise to many problems, including one of signal crosstalk.
Signal crosstalk means interference between signals that is apt to arise between a plurality of wires arranged in positions physically close to each other. Generally, integrated circuits and systems are designed to enable the functions to be processed by their circuits to be completed within prescribed lengths of delay time so that they can operate at the target frequency given by the respective specifications.
If they are designed without taking into account the crosstalk mentioned above, the variations in delay time invited by the interference between signals will be overlooked, and this might make it impossible for the semiconductor integrated circuit chips or the systems to operate at their respective target frequencies. To avoid such a consequence, there is needed a method by which delay degradations due to crosstalk can be analyzed precisely.
Such crosstalk analysis methods are disclosed in the Japanese Patent Laid-open No. H7-98727, Japanese Patent Laid-open No. H11-40677 and Japanese Patent Laid-open No. H11-154709.
Although the above-cited methods according to the prior art are effective for crosstalk analysis, they are subject to various constraints in actual application to the designing of a delicate and large-scale electronic circuit device because they are based on limiting conditions, and therefore it is difficult to apply them to the designing of actual, complex electronic circuit devices.
For instance, since there is a constraint on the signal transition time of aggressor wires, it can be mentioned that the signal arrival time of a victim wire and that of an aggressor wire greatly influences the delay time. Another constraint is the dynamic dependence of the arrival time of a signal at each wire on its input pattern, which makes it particularly difficult to calculate accurately and efficiently the delay time due to crosstalk in a high-speed and large-scale electronic circuit device in which a large number of aggressor wires are present.
The present invention is intended to provide a novel crosstalk analysis method for solving these problems, and thereby to make it possible to design and manufacture high-speed and large-scale electronic circuit devices realistically and efficiently.
More specifically, the invention is intended to provide a novel method, for use with high-speed and large-scale electronic circuit devices in which, adjacent to one victim wire, a plurality of other wires are arranged, to calculate accurately and efficiently the crosstalk-deriving complex delay degradation that this plurality of aggressor wires inflict on the victim wire.
As explained above, what poses difficulty in crosstalk analysis is the dependence of its impact on the signal arrival time.
In view of this point, the present inventors proposed in xe2x80x9cCross-talk Delay Analysis using Relative Window Method,xe2x80x9d Proceedings of IEEE International ASIC/SOC Conference 1999, pp. 9-13 (hereinafter abbreviated to RWM or referred to as Reference 1), a new analysis method for overcoming these constraints.
Thus, as shown in FIG. 1, the problem is that, depending on the relative timing between the signal arrival time on a wire 3 whose delay time is to be analyzed (hereinafter referred to as victim wire or Victim) (hereinafter referred to as VSAT: victim signal arrival time) and the signal arrival time on a wire 4 interfering with it (hereinafter referred to as aggressor wire or Aggressor) (hereinafter referred to as ASAT: aggressor signal arrival time), the delay time varies in many different ways and thereby invites a delay degradation (hereinafter its magnitude will be referred to as delay degradation value).
Incidentally, here is deliberate taken up a case in which the signals reaching at the respective nodes of wires are in a relationship of out-phase-transition as shown in the left part of FIG. 1. Although there would be no difference in basic idea even if those signals were in a relationship of in-phase-transition, the delay time would be shorter than in the case of out-phase-transition.
In this Reference 1, in considering the influence of the signal arrival time, a relative signal arrival time (hereinafter referred to as RSAT: relative signal arrival time) which is obtained by assessing the ASAT with reference to the VSAT, is used. Here is prepared in advance a graph or table of delay degradation values with the relative signal arrival time RSAT represented on the horizontal axis as shown in FIG. 2 for each combination of drivers for the victim and the aggressor (e.g. NAND gate output drive circuits), and the delay degradation value is calculated for each actual case with reference to this graph or table.
A factor further complicating this problem is that the VSAT and the ASAT themselves dynamically vary, dependent on the input patterns (including paths) of the respective arriving signals. FIG. 3 illustrates this point. For instance, in one type of input pattern variation, whereas the signal is transmitted from an input node in1 to a node n2 via a node n1, the signal arrival time at the n2 point in this case is 0.40 ns. In another type of input pattern variation, however, the signal is transmitted from in3 to n2, and the signal arrival time at the n2 point in this case is 0.10 ns, different from the value mentioned above. Since the RSAT cannot be uniquely determined for this reason, the degradation graph or table such as the one shown in FIG. 2 cannot be simply applied.
The technique proposed in Reference addresses this problem by resorting to a concept known as the relative window.
The method is illustrated in FIGS. 4(a), 4(b) and 4(c). Since the VSAT and the ASAT dynamically vary with the input pattern, neither of them can be obtained as one point of time. Therefore, as shown in FIG. 4(a), the VSAT and the ASAT are calculated as windows each having a range (or width) of time in which a signal has a possibility of actually arriving. The windows will be referred to as the VSAT window and the ASAT window, respectively.
Next, as the RSAT cannot be determined uniquely, instead it is calculated as a window having a width (hereinafter referred to as relative window) as shown in FIG. 4(b). The relative window here means the range from a time when the RSAT is at its minimum to a time when the RSAT is at its maximum. It is when the ASAT is at its minimum and the VSAT is at its maximum that the RSAT is at its minimum. Conversely, the RSAT is at its maximum when the ASAT is at its maximum and the VSAT is at its minimum. Thus, Min (RSAT)=Min (ASAT)xe2x88x92Max (VSAT) and Max (RSAT)=Max (ASAT)xe2x88x92Min (VSAT).
Then, as shown in FIG. 4(c), a quantified delay degradation value can be figured out by obtaining the worst delay degradation value within the relative window RSAT range from the relative window RSAT thereby calculated and the aforementioned degradation graph or table prepared in advance.
The delay degradation value obtained in this way very well agrees with the result of simulation in an actual circuit and is highly accurate.
Incidentally, generally speaking, in the wiring part of a large-scale semiconductor integrated circuit or an electronic circuit device mounted on a substrate there may be more than one aggressor wire per victim wire. In other words, crosstalk may occur between a plurality of aggressor wires and a single victim wire.
However, it has been found that, where there are a plurality of aggressor wires against a single victim wire as stated above, application of the crosstalk analysis technique of Reference 1 would give rise to a problem.
Next, using FIGS. 5(a) through 5(d), this problem will be discussed on the basis of an analysis technique by which the present inventors actually calculated with reference to an example in which there were two aggressor wires against a single victim wire.
FIG. 5(a) shows the signal arrival time ranges of the one victim wire and the two aggressor wires on a time axis. (hereinafter referred to as VSAT, ASAT 1 and ASAT 2, respectively). FIGS. 5(b) and 5(c) show the relationship between the range in which a delay degradation arises between the one victim wire and each aggressor wire (hereinafter referred to as crosstalk range) and the relative window for each of the aggressor wires, with the vertical-axis representing the delay degradation value.
First, the delay degradation value is calculated for each aggressor wire by using the analysis technique of Reference land, from the delay degradation value characteristic diagrams of FIGS. 5(b) and 5(c), DD1 is obtained as the delay degradation value in the worst case between a first aggressor wire (Aggressor 1) and the victim wire (Victim), and DD2, as the delay degradation value in the worst case between a second aggressor wire (Aggressor 2) and the victim wire (Victim).
Next, as shown in FIG. 5(d), the worst delay degradation values obtained for the different aggressor wires are added to find out the total delay degradation value of all the aggressor wires (DD(total)=xcexa3DDi=DD1+DD2).
While the calculation procedure described above makes possible estimation of the delay degradation value even in the presence of a plurality of aggressor wires, this method involves the following problem.
Thus, the resultant delay degradation value may prove considerably greater than the worst that can really occur. This point will be explained with reference to FIGS. 5 cited above.
It is supposed that here, as shown in FIG. 5(a), Victim and Aggressor 1 give rise to the worst case under the condition of Tv1=5.0 ns and Victim and Aggressor 2 do so under the condition of Tv2=7.5 ns. Simple totalization of the delay degradation values in both worst cases means supposition of the simultaneous occurrence of these two conditions.
Certainly, supposing that the worst cases of the delay degradation value for the two pairs of the victim wire and an aggressor wire do occur at the same time, the total of those delay degradation values would be the worst. In reality, however, these two conditions can never occur at the same time, because Victim is the same wire in the two cases, the signal arrival time VSAT cannot take two unrelated different values at the same time (even if there is a difference in signal propagation time, the different time values cannot be totally unrelated to each other).
This means that the above-described technique, which presupposes that the worst cases can occur at the same time for the two pairs of different aggressor wires and the common victim wire, takes into account what can never occur in reality, and therefore overestimates the delay degradation value. This can pose a serious problem especially where the number of aggressor wires is great.
The present invention is intended to provide a method for analyzing more accurately and efficiently crosstalk-deriving delay degradation values where there are a plurality of aggressor wires and the signal arrival time of each of a victim wire and aggressor wires dynamically varies dependent on input pattern variations (including path variations).
More specifically, the invention is intended to provide a designing technique which makes possible designing and manufacturing of an electronic circuit device with a reduced margin, in figuring out delay degradations due to crosstalk inflicted by a plurality of aggressor wires on a single victim wire, for extra delay time which cannot arise in the operation of any actual electronic circuit.
Some of the typical aspects of the invention disclosed in the present application will be briefly summarized below.
Thus according to the invention, there is provided an analysis method for crosstalk-deriving delay degradations for use where there are a plurality of aggressor wires (Aggressors) against a single victim wire (Victim) and the signal arrival time of each of a victim wire and aggressor wires dynamically varies dependent on input pattern variations (including path variations) (called MA-RWM (Multi-Aggressor Relative Window Method) as distinguished from RWM described above).
In analyzing delay degradations, simple application of the method described in Reference 1 would also involve cases which cannot really occur because the VSAT as the absolute time is not taken into account, but according to the present invention, which excludes from analysis such impossible cases, the delay degradation characteristics which dynamic variations in signal arrival on each aggressor wire bring to bear on a specific victim wire are figured out, these delay degradation are added on the basis of the signal arrival time on the victim wire, and crosstalk in the presence of a plurality of Aggressors is thereby made analyzable with high accuracy.